The present invention relates to MOSFET devices. Even more particularly, the present invention relates to MOSFET devices with a raised (or elevated) source and a raised drain (raised S/D).
In the prior art, deep source and drain (deep source/drain) contact junctions are desirable to allow silicidation of the source and drain. Silicidation is the process of combining silicon with a metal such as titanium forming titanium silicide TiSi2. Silicides provide the advantages of being stable during contact with polysilicon and having a lower RC time delay than silicon. A lower RC time delay is important in high speed circuits. In opposition, shallow source and drain (source/drain) extensions are desirable to provide immunity to the xe2x80x9cshort-channel effectxe2x80x9d, One cause for the short-channel effect is that as MOSFET devices are made with shorter gate lengths, the depletion layer widths of the source and drain junction become comparable to channel length, resulting in punch-through, where the gate loses control of the current. To obtain the benefits from deep source and drain contact junctions and shallow source/drain extensions the raised (or elevated) source/drain structure is used.
In the prior art, shallow source and drain extensions are first formed on a substrate. Pure Silicon (Si) selective epitaxy growth (SEG) is then used to form an elevated source and an elevated drain (elevated source/drain). The selective Si epitaxy process done in the prior art is a high temperature ( greater than 900xc2x0 C.) process. This high temperature process causes further diffusion of the source/drain extensions making the source/drain extensions deep, which degrades transistor short channel performance.
The prior art also teaches the use of Silicon Germanium (SiGe) selective epitaxy growth (SEG) to form raised source/drain, using a 5-10% Germanium (Ge) concentration. This process uses a temperature that is 100-200xc2x0 C. lower than the temperature used in the pure Si selective epitaxy growth, allowing for shallow source/drain extensions. In addition, SiGe provides improved epitaxy selectivity between Silicon and dielectric in the trench isolation and spacer region. A problem with the use of SiGe selective epitaxy growth is that a 5-10% concentration of Ge in the raised source/drain region makes the silicidation of the raised source/drain difficult.
It is an object of the invention to provide a lower temperature epitaxy growth with improved selectivity, to provide raised source/drains without silicidation problems.
Accordingly, the foregoing object is accomplished by providing a method and apparatus for performing SiGe epitaxy where the concentration of Germanium to Silicon is gradually reduced from above 5% to close to 0% during the epitaxy process, resulting in a device with raised source/drains which have the highest concentration (5-10%) of Germanium near the bottom of the source/drain and gradually reduced to 0% Germanium near the top of the source/drain.
The higher concentration of Germanium near the bottom of the source/drain helps to provide good epitaxy selectivity over other parts of the device area, such as trench isolation and gate stack dielectric spacers. The lower concentration of Germanium near the top of the source/drain allows for an easier silicidation of the source/drain. The lower temperature (100-200xc2x0 C. below temperatures used in pure Si epitaxy), can be maintained even when the Germanium concentration becomes zero, since as long as SiGe seed has been formed, the Germanium concentration may be gradually reduced without raising temperature.
Other features of the present invention are disclosed or apparent in the section entitled: xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d